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Senior Digital Design Engineer (W/M)

As subsidiary of an industrial group based in Grenoble, IC’Alps designs analog and digital integrated circuits (“ASIC – Application Specific Integrated Circuit”) for the other units of the group and external customers: 50% for medical applications, and 50% for consumer, automotive, industrial and other markets… Bringing together recognized experts in France, we are experiencing rapid growth and, to reinforce our digital team, are looking for:

Senior Digital Design Engineer (W/M)

Your missions

  • Consolidating the link between digital design and physical implementation, a fundamental position in the constant search for being right at the first path.

    In a team of 10-12 digital designers (concentrating design, verification, and physical implementation skills) and in the frame of projects for mixed ASIC (analog/digital):

    • You study, specify and design digital blocks, sub-systems (e.g. around an embedded processor or a memory sub-system…) and/or top level, making area/power estimations
    • You elaborate testability insertion strategy corresponding to the circuit specifications
    • You perform verification tasks (coverage rate, unit block simulation, complete system simulation, mixed analog / logic simulation, functional and test modes…) until the generation of test patterns for silicon measurements in our lab.
    • You improve the digital design, functional and test mode verification flow
    • You perform digital synthesis and Design for Test (DfT), using techniques that reduce the difficulty and cost associated when testing an integrated circuit (with the use on scan compression, built-in self-test (BIST) or increased observability using JTAG…)
    • You lead, debate and present the choice of architectures and design status during review meetings within the ASIC project team and in front of customers.

Your Profile

  • Engineering degree (or equivalent) in microelectronics
  • First significant experience (> 5 years) in Front-end ASIC digital design in VHDL and/or Verilog and/or SystemVerilog, and in digital synthesis for DFT
  • Comfortable in scripting (python, tcl, …)
  • Experience with seeing a project through from beginning to completion with strong customer interaction
  • Excellent analytical and problem-solving skills
  • Ability to work independently but with a strong team spirit, while being a real force of proposals
  • Leadership and strong written and verbal communication skills
  • Curiosity, interest for final applications, rigor and requirement in the quality of work
  • Fluent English / Nice to have: French
  • Bonuses: knowledge of different tools (Mentor, Synopsys, Cadence), design in different languages (SystemVerilog, VHDL, …), experience in mixed ASIC environment.

Conditions

  • Type of employment: permanent, full time
  • Location: Grenoble (Saint Martin d’Hères) – France
  • Salary: competitive package, depending on the profile

The most of the position:
You will join a group in which you can have an impact, with growing perspectives, fast and reactive in its decisions. Our team members are ambitious in their objectives, opened in their operation. And the working environment is pleasant!

So, if you like to join a design team fully dedicated to the success of the project, from the requirements specifications serving customers’ applications, to the measurements on silicon and the production monitoring, if you are curious and motivated to learn new skills and share your own, do not hesitate!

Join a dynamic company to take technical challenges as a team, in designing integrated circuits for diverse application needs, and apply by sending us your resume and cover letter.

Submit your resume