Physical Implementation Engineer

As subsidiary of an industrial group based in Grenoble, IC’Alps designs analog and digital integrated circuits (“ASIC”) for the other units of the group and external customers: 50% for medical applications, and 50% for consumer, automotive, industrial and other markets… Bringing together recognized experts in France, we are experiencing rapid growth and, to reinforce our digital team, are looking for:

A Physical Implementation Engineer (W/M)

Your missions

As part of an ASIC/SoC design activity or integrated circuits for diversified applications, and in interaction with the different actors of a project and experts required (analog or digital design,…) you will take care of everything or part of the different steps of a physical implementation: synthesis, DfT, floorplan, clock tree synthesis, place & route and verifications (STA, consumption analysis, thermal analysis, proof of equivalence, DRC, LVS, IR- Drop).

Your missions will be more precisely the following ones:

Realization of integrated circuits from RTL up to GDSII
Definition and Implementation of DfT on complex digital partitions or top up to the generation and verification of test patterns for industrial test program
Establishment of timing constraints in consultation with the designer of the RTL code and the architect of the circuit
Set up environments and synthesis / DfT / Place & Route flows to realize low voltage and low power implementations
Realization of the steps for database validation
Development of checklists in accordance with ISO9001 / ISO13485 / EN9100 requirements
Exploration for commitment to speed, consumption and surface performances
Participation in the development of a physical implementation kit with the set-up of scripts and checklists.

Your Profile

Engineering degree (or equivalent) in microelectronics
Minimum 5 years’ experience in one major step of physical implementation (DfT or place & route + STA ) with: ability to set up a flow for a circuit of a certain complexity or in a new environment, knowledge of several technologies from 180nm down to 22FDX (and more advanced is a plus), autonomy in TCL scripts (Python would be a plus), ability to write timing constraints, UPF / CPF files.
Curiosity, resistance to stress, rigor in the quality of work, ease of communication, analytical and synthesis spirit and strength of proposals
Fluent English / Nice to have: French
Bonuses: Mastery of at least one P&R tool (ICC2 – Synopsys, Innovus-Cadence), static timing analysis (PrimeTime,…), logical synthesis (Design Compiler,…), DfT (Tessent), logic or analog or mixed simulation for electrical simulations, IR-Drop analysis.

Conditions

Type of employment: permanent, full time
Location : Grenoble (Saint Martin d’Hères) – France
Salary: between €45,000 and €65,000 per year, depending on the profile

The most of the position:
You will join a group in which the ideas of each one are examined, rigorous at work, fast in their decisions, ambitious in their objectives, opened in their operation.
So, if you like to join a design team fully dedicated to the success of the project, from the requirements specifications serving customers’ applications, to the measurements on silicon and the production monitoring, if you are curious and motivated to learn new skills and share your own, do not hesitate!

Join a dynamic company to take technical challenges as a team, in designing integrated circuits for diverse application needs, and apply by sending us your resume and cover letter.