The customer requested IC’Alps design services for the realization of the layout and virtual characterization of asynchronous standard cell libraries (> 60 cells) for TSMC 16nm FFC (FinFET Compact) and GF22nm FDX technologies.
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Built-in measures at IC level ensure an unprecedented level of digital security for all devices but remain sensitive to clock tempering when synchrone. IC’Alps was asked to design parts of an asynchronous standard cells (SC) librairy for Embedded security IP (or Secure Elements).
After the successfull completion of this service, the Customer requested an Asynchronous Secured IP block implementation.
The customer requested IC’Alps design services for the realization of the layout and virtual characterization of asynchronous standard cell libraries (> 60 cells) for TSMC 16nm FFC (FinFET Compact) and GF22nm FDX technologies.
We first developed and validated the simulation/characterization environment for the two targeted technologies (TSMC 16nm and GF 22 nm).
In parallel, we started the layout of the asynchronous standard cells in TSMC 16FFC from Customer schematics.
Then came the layout of the cells with sizing optimization, schematic validation loops with Customer and verification of cells usability through abutment and routability tests.
The Team then delivered a backend view database including GDSII, OA database and spice netlist with parasitic.
With the extracted spice netlists, a characterization of the different asynchronous standard cell libraries was performed: in TSMC 16nm and GF 22 nm, 10 corners SVT/LVT. Finally, the Team delivered compiled Liberty views and, for TSMC 16FFC, self-heating aware IR-drop validation requirements, TRF model have been delivered too.
This project allowed our Team to gain considerable characterization expertise.